ARM architecture family
ARM (stylised in lowercase as arm, formerly an acronym for Advanced RISC Machines and originally Acorn RISC Machine) is a family of RISC instruction set architectures (ISAs) for computer processors. Arm Ltd. develops the ISAs and licenses them to other companies, who build the physical devices that use the instruction set. It also designs and licenses cores that implement these ISAs.
"ARM architecture" redirects here. For the Australian architectural firm, see ARM Architecture (company).Designer
1985
Condition code, compare and branch
Proprietary
2011
ARMv8-R, ARMv8-A, ARMv8.1-A, ARMv8.2-A, ARMv8.3-A, ARMv8.4-A, ARMv8.5-A, ARMv8.6-A, ARMv8.7-A, ARMv8.8-A, ARMv8.9-A, ARMv9.0-A, ARMv9.1-A, ARMv9.2-A, ARMv9.3-A, ARMv9.4-A
Bi (little as default)
31 × 64-bit integer registers[1]
ARMv9-R, ARMv9-M, ARMv8-R, ARMv8-M, ARMv7-A, ARMv7-R, ARMv7E-M, ARMv7-M, ARMv6-M
32-bit, except Thumb-2 extensions use mixed 16- and 32-bit instructions.
Bi (little as default)
15 × 32-bit integer registers, including R14 (link register), but not R15 (PC)
Up to 32 × 64-bit registers,[2] SIMD/floating-point (optional)
ARMv6, ARMv5, ARMv4T, ARMv3, ARMv2
32-bit, except Thumb extension uses mixed 16- and 32-bit instructions.
Bi (little as default) in ARMv3 and above
15 × 32-bit integer registers, including R14 (link register), but not R15 (PC, 26-bit addressing in older)
None
Due to their low costs, low power consumption, and low heat generation, ARM processors are useful for light, portable, battery-powered devices, including smartphones, laptops, and tablet computers, as well as embedded systems.[3][4][5] However, ARM processors are also used for desktops and servers, including the world's fastest supercomputer (Fugaku) from 2020[6] to 2022. With over 230 billion ARM chips produced,[7][8][9] as of 2022, ARM is the most widely used family of instruction set architectures.[10][4][11][12][13]
There have been several generations of the ARM design. The original ARM1 used a 32-bit internal structure but had a 26-bit address space that limited it to 64 MB of main memory. This limitation was removed in the ARMv3 series, which has a 32-bit address space, and several additional generations up to ARMv7 remained 32-bit. Released in 2011, the ARMv8-A architecture added support for a 64-bit address space and 64-bit arithmetic with its new 32-bit fixed-length instruction set.[14] Arm Ltd. has also released a series of additional instruction sets for different rules; the "Thumb" extension adds both 32- and 16-bit instructions for improved code density, while Jazelle added instructions for directly handling Java bytecode. More recent changes include the addition of simultaneous multithreading (SMT) for improved performance or fault tolerance.[15]
Arm SystemReady, formerly named Arm ServerReady, is a certification program that helps land the generic off-the-shelf operating systems and hypervisors on to the Arm-based systems from datacenter servers to industrial edge and IoT devices. The key building blocks of the program are the specifications for minimum hardware and firmware requirements that the operating systems and hypervisors can rely upon. These specifications are:[166]
These specifications are co-developed by Arm and its partners in the System Architecture Advisory Committee (SystemArchAC).
Architecture Compliance Suite (ACS) is the test tools that help to check the compliance of these specifications. The Arm SystemReady Requirements Specification documents the requirements of the certifications.[171]
This program was introduced by Arm in 2020 at the first DevSummit event. Its predecessor Arm ServerReady was introduced in 2018 at the Arm TechCon event. This program currently includes four bands:
PSA Certified[edit]
PSA Certified, formerly named Platform Security Architecture, is an architecture-agnostic security framework and evaluation scheme. It is intended to help secure Internet of things (IoT) devices built on system-on-a-chip (SoC) processors.[172] It was introduced to increase security where a full trusted execution environment is too large or complex.[173]
The architecture was introduced by Arm in 2017 at the annual TechCon event.[173][174] Although the scheme is architecture agnostic, it was first implemented on Arm Cortex-M processor cores intended for microcontroller use. PSA Certified includes freely available threat models and security analyses that demonstrate the process for deciding on security features in common IoT products.[175] It also provides freely downloadable application programming interface (API) packages, architectural specifications, open-source firmware implementations, and related test suites.[176]
Following the development of the architecture security framework in 2017, the PSA Certified assurance scheme launched two years later at Embedded World in 2019.[177] PSA Certified offers a multi-level security evaluation scheme for chip vendors, OS providers and IoT device makers.[178] The Embedded World presentation introduced chip vendors to Level 1 Certification. A draft of Level 2 protection was presented at the same time.[179] Level 2 certification became a usable standard in February 2020.[180]
The certification was created by PSA Joint Stakeholders to enable a security-by-design approach for a diverse set of IoT products. PSA Certified specifications are implementation and architecture agnostic, as a result they can be applied to any chip, software or device.[181][179] The certification also removes industry fragmentation for IoT product manufacturers and developers.[182]
, ARM Ltd.
