Designer

32-bit, 64-bit

1985 (1985)

RISC

Register-Register

Condition code, compare and branch

Proprietary

ARMv9-R, ARMv9-M, ARMv8-R, ARMv8-M, ARMv7-A, ARMv7-R, ARMv7E-M, ARMv7-M, ARMv6-M

32-bit, except Thumb-2 extensions use mixed 16- and 32-bit instructions.

Bi (little as default)

Thumb-2, Neon, Jazelle, AES, SHA, DSP, Saturated, FPv4-SP, FPv5, Helium

15 × 32-bit integer registers, including R14 (link register), but not R15 (PC)

Up to 32 × 64-bit registers,[2] SIMD/floating-point (optional)

Katana VentraIP

ARM architecture family

ARM (stylised in lowercase as arm, formerly an acronym for Advanced RISC Machines and originally Acorn RISC Machine) is a family of RISC instruction set architectures (ISAs) for computer processors. Arm Ltd. develops the ISAs and licenses them to other companies, who build the physical devices that use the instruction set. It also designs and licenses cores that implement these ISAs.

Version

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