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Dynamic random-access memory

Dynamic random-access memory (dynamic RAM or DRAM) is a type of random-access semiconductor memory that stores each bit of data in a memory cell, usually consisting of a tiny capacitor and a transistor, both typically based on metal–oxide–semiconductor (MOS) technology. While most DRAM memory cell designs use a capacitor and transistor, some only use two transistors. In the designs where a capacitor is used, the capacitor can either be charged or discharged; these two states are taken to represent the two values of a bit, conventionally called 0 and 1. The electric charge on the capacitors gradually leaks away; without intervention the data on the capacitor would soon be lost. To prevent this, DRAM requires an external memory refresh circuit which periodically rewrites the data in the capacitors, restoring them to their original charge. This refresh process is the defining characteristic of dynamic random-access memory, in contrast to static random-access memory (SRAM) which does not require data to be refreshed. Unlike flash memory, DRAM is volatile memory (vs. non-volatile memory), since it loses its data quickly when power is removed. However, DRAM does exhibit limited data remanence.

"DRAM" redirects here. For other uses, see Dram.

DRAM typically takes the form of an integrated circuit chip, which can consist of dozens to billions of DRAM memory cells. DRAM chips are widely used in digital electronics where low-cost and high-capacity computer memory is required. One of the largest applications for DRAM is the main memory (colloquially called the "RAM") in modern computers and graphics cards (where the "main memory" is called the graphics memory). It is also used in many portable devices and video game consoles. In contrast, SRAM, which is faster and more expensive than DRAM, is typically used where speed is of greater concern than cost and size, such as the cache memories in processors.


The need to refresh DRAM demands more complicated circuitry and timing than SRAM. This is offset by the structural simplicity of DRAM memory cells: only one transistor and a capacitor are required per bit, compared to four or six transistors in SRAM. This allows DRAM to reach very high densities with a simultaneous reduction in cost per bit. Refreshing the data consumes power and a variety of techniques are used to manage the overall power consumption.


DRAM had a 47% increase in the price-per-bit in 2017, the largest jump in 30 years since the 45% jump in 1988, while in recent years the price has been going down.[3] In 2018, a "key characteristic of the DRAM market is that there are currently only three major suppliers — Micron Technology, SK Hynix and Samsung Electronics" that are "keeping a pretty tight rein on their capacity".[4] There is also Kioxia (previously Toshiba Memory Corporation after 2017 spin-off). Other manufacturers make and sell DIMMs (but not the DRAM chips in them), such as Kingston Technology, and some manufacturers that sell stacked DRAM (used e.g. in the fastest supercomputers on the exascale), separately such as Viking Technology. Others sell such integrated into other products, such as Fujitsu into its CPUs, AMD in GPUs, and Nvidia, with HBM2 in some of their GPU chips.

RAS, the Row Address Strobe. The address inputs are captured on the falling edge of RAS, and select a row to open. The row is held open as long as RAS is low.

CAS, the Column Address Strobe. The address inputs are captured on the falling edge of CAS, and select a column from the currently open row to read or write.

WE, Write Enable. This signal determines whether a given falling edge of CAS is a read (if high) or write (if low). If low, the data inputs are also captured on the falling edge of CAS.

OE, Output Enable. This is an additional signal that controls output to the data I/O pins. The data pins are driven by the DRAM chip if RAS and CAS are low, WE is high, and OE is low. In many applications, OE can be permanently connected low (output always enabled), but switching OE can be useful when connecting multiple memory chips in parallel.

DRAM price fixing scandal

Flash memory

List of interface bit rates

Memory bank

Memory geometry

Keeth, Brent; Baker, R. Jacob; Johnson, Brian; Lin, Feng (2007). . Wiley. ISBN 978-0470184752.

DRAM Circuit Design: Fundamental and High-Speed Topics

Jacob, Bruce; Wang, David; Ng, Spencer (2010) [2008]. . Morgan Kaufmann. ISBN 978-0-08-055384-9.

Memory Systems: Cache, DRAM, Disk

Culler, David (2005). "Memory Capacity (Single Chip DRAM)". . Electrical Engineering and Computer Sciences,University of California, Berkeley. p. 15. Logarithmic graph 1980–2003 showing size and cycle time.

EECS 252 Graduate Computer Architecture: Lecture 1

— A 1997 discussion of SDRAM reliability—some interesting information on "soft errors" from cosmic rays, especially with respect to error-correcting code schemes

Benefits of Chipkill-Correct ECC for PC Server Main Memory

1994 literature review of memory error rate measurements.

Tezzaron Semiconductor Soft Error White Paper

Johnston, A. (October 2000). (PDF). 4th Annual Research Conference on Reliability Stanford University. Archived from the original (PDF) on 2004-11-03.

"Scaling and Technology Issues for Soft Error Rates"

Mandelman, J. A.; Dennard, R. H.; Bronner, G. B.; Debrosse, J. K.; Divakaruni, R.; Li, Y.; Radens, C. J. (2002). . IBM Journal of Research and Development. 46 (2.3): 187–212. doi:10.1147/rd.462.0187. Archived from the original on 2005-03-22.

"Challenges and future directions for the scaling of dynamic random-access memory (DRAM)"

Ars Technica: RAM Guide

Wang, David Tawei (2005). (PDF) (PhD). University of Maryland, College Park. hdl:1903/2432. Retrieved 2007-03-10. A detailed description of current DRAM technology.

Modern DRAM Memory Systems: Performance Analysis and a High Performance, Power-Constrained DRAM-Scheduling Algorithm

Multi-port Cache DRAM — MP-RAM

Drepper, Ulrich (2007). .

"What every programmer should know about memory"