Gate array
A gate array is an approach to the design and manufacture of application-specific integrated circuits (ASICs) using a prefabricated chip with components that are later interconnected into logic devices (e.g. NAND gates, flip-flops, etc.) according to custom order by adding metal interconnect layers in the factory. It was popular during the upheaval in the semiconductor industry in the 1980s, and its usage declined by the end of the 1990s.
Similar technologies have also been employed to design and manufacture analog, analog-digital, and structured arrays, but, in general, these are not called gate arrays.
Gate arrays have also been known as uncommitted logic arrays (ULAs), which also offered linear circuit functions,[1] and semi-custom chips.
History[edit]
Development[edit]
Gate arrays had several concurrent development paths. Ferranti in the UK pioneered commercializing bipolar ULA technology,[2] offering circuits of "100 to 10,000 gates and above" by 1983.[3][4] The company's early lead in semi-custom chips, with the initial application of a ULA integrated circuit involving a camera from Rollei in 1972, expanding to "practically all European camera manufacturers" as users of the technology, led to the company's dominance in this particular market throughout the 1970s. However, by 1982, as many as 30 companies had started to compete with Ferranti, reducing the company's market share to around 30 percent. Ferranti's "major competitors" were other British companies such as Marconi and Plessey, both of which had licensed technology from another British company, Micro Circuit Engineering.[5] A contemporary initiative, UK5000, also sought to produce a CMOS gate array with "5,000 usable gates", with involvement from British Telecom and a number of other major British technology companies.[6]
IBM developed proprietary bipolar master slices that it used in mainframe manufacturing in the late 1970s and early 1980s, but never commercialized them externally. Fairchild Semiconductor also flirted briefly in the late 1960s with bipolar arrays diode–transistor logic and transistor-transistor logic called Micromosaic and Polycell.[7]
CMOS (complementary metal–oxide–semiconductor) technology opened the door to the broad commercialization of gate arrays. The first CMOS gate arrays were developed by Robert Lipp[8][9] in 1974 for International Microcircuits, Inc.[7] (IMI) a Sunnyvale photo-mask shop started by Frank Deverse, Jim Tuttle and Charlie Allen, ex-IBM employees. This first product line employed 7.5 micron single-level metal CMOS technology and ranged from 50 to 400 gates. Computer-aided design (CAD) technology at the time was very rudimentary due to the low processing power available, so the design of these first products was only partially automated.
This product pioneered several features that went on to become standard in future designs. The most important were: the strict organization of n-channel and p-channel transistors in 2-3 row pairs across the chip; and running all interconnect on grids rather than minimum custom spacing, which had been the standard until then. This later innovation paved the way to full automation when coupled with the development of 2-layer CMOS arrays. Customizing these first parts was somewhat tedious and error-prone due to the lack of good software tools.[7] IMI tapped into PC board development techniques to minimize manual customization effort. Chips at the time were designed by hand, drawing all components and interconnecting on precision gridded Mylar sheets, using colored pencils to delineate each processing layer. Rubylith sheets were then cut and peeled to create a (typically) 200x to 400x scale representation of the process layer. This was then photo-reduced to make a 1x mask. Digitization rather than rubylith cutting was just coming in as the latest technology, but initially, it only removed the rubylith stage; drawings were still manual and then "hand" digitized. PC boards, meanwhile, had moved from custom rubylith to PC tape for interconnects. IMI created to-scale photo enlargements of the base layers. Using decals of logic gate connections and PC tape to interconnect these gates, custom circuits could be quickly laid out by hand for these relatively small circuits, and photo-reduced using existing technologies.
After a falling out with IMI, Robert Lipp went on to start California Devices, Inc. (CDI) in 1978 with two silent partners, Bernie Aronson, and Brian Tighe. CDI quickly developed a product line competitive to IMI and, shortly thereafter, a 5-micron silicon gate single-layer product line with densities of up to 1,200 gates. A couple of years later, CDI followed up with "channel-less" gate arrays that reduced the row blockages caused by a more complex silicon underlayer that pre-wired the individual transistor connections to locations needed for common logic functions, simplifying the first-level metal interconnect. This increased chip densities by 40%, significantly reducing manufacturing costs.[8]
