Semiconductor device fabrication
Semiconductor device fabrication is the process used to manufacture semiconductor devices, typically integrated circuits (ICs) such as computer processors, microcontrollers, and memory chips (such as NAND flash and DRAM). It is a multiple-step photolithographic and physico-chemical process (with steps such as thermal oxidation, thin-film deposition, ion-implantation, etching) during which electronic circuits are gradually created on a wafer, typically made of pure single-crystal semiconducting material. Silicon is almost always used, but various compound semiconductors are used for specialized applications.
The fabrication process is performed in highly specialized semiconductor fabrication plants, also called foundries or "fabs",[1] with the central part being the "clean room". In more advanced semiconductor devices, such as modern 14/10/7 nm nodes, fabrication can take up to 15 weeks, with 11–13 weeks being the industry average.[2] Production in advanced fabrication facilities is completely automated, with automated material handling systems taking care of the transport of wafers from machine to machine.[3]
A wafer often has several integrated circuits which are called dies as they are pieces diced from a single wafer. Individual dies are separated from a finished wafer in a process called die singulation, also called wafer dicing. The dies can then undergo further assembly and packaging.[4]
Within fabrication plants, the wafers are transported inside special sealed plastic boxes called FOUPs.[3] FOUPs in many fabs contain an internal nitrogen atmosphere[5][6] which helps prevent copper from oxidizing on the wafers. Copper is used in modern semiconductors for wiring.[7] The insides of the processing equipment and FOUPs is kept cleaner than the surrounding air in the cleanroom. This internal atmosphere is known as a mini-environment and helps improve yield which is the amount of working devices on a wafer. This mini environment is within an EFEM (equipment front end module)[8] which allows a machine to receive FOUPs, and introduces wafers from the FOUPs into the machine. Additionally many machines also handle wafers in clean nitrogen or vacuum environments to reduce contamination and improve process control.[3] Fabrication plants need large amounts of liquid nitrogen to maintain the atmosphere inside production machinery and FOUPs, which are constantly purged with nitrogen.[5][6] There can also be an air curtain or a mesh[9] between the FOUP and the EFEM which helps reduce the amount of humidity that enters the FOUP and improves yield.[10][11]
Companies that manufacture machines used in the industrial semiconductor fabrication process include ASML, Applied Materials, Tokyo Electron and Lam Research.
Feature size[edit]
Feature size is determined by the width of the smallest lines that can be patterned in a semiconductor fabrication process, this measurement is known as the linewidth.[12][13] Patterning often refers to photolithography which allows a device design or pattern to be defined on the device during fabrication.[14] F2 is used as a measurement of area for different parts of a semiconductor device, based on the feature size of a semiconductor manufacturing process. Many semiconductor devices are designed in sections called cells, and each cell represents a small part of the device such as a memory cell to store data. Thus F2 is used to measure the area taken up by these cells or sections.[15]
A specific semiconductor process has specific rules on the minimum size (width or CD/Critical Dimension) and spacing for features on each layer of the chip.[16]
Normally a new semiconductor process has smaller minimum sizes and tighter spacing. In some cases, this allows a simple die shrink of a currently produced chip design to reduce costs, improve performance,[16] and increase transistor density (number of transistors per unit area) without the expense of a new design.
Early semiconductor processes had arbitrary names for generations (viz., HMOS I/II/III/IV and CHMOS III/III-E/IV/V). Later each new generation process became known as a technology node[17] or process node,[18][19] designated by the process' minimum feature size in nanometers (or historically micrometers) of the process's transistor gate length, such as the "90 nm process". However, this has not been the case since 1994,[20] and the number of nanometers used to name process nodes (see the International Technology Roadmap for Semiconductors) has become more of a marketing term that has no standardized relation with functional feature sizes or with transistor density (number of transistors per unit area).[21]
Initially transistor gate length was smaller than that suggested by the process node name (e.g. 350 nm node); however this trend reversed in 2009.[20] Feature sizes can have no connection to the nanometers (nm) used in marketing.
For example, Intel's former 10 nm process actually has features (the tips of FinFET fins) with a width of 7 nm, so the Intel 10 nm process is similar in transistor density to TSMC's 7 nm process. As another example, GlobalFoundries' 12 and 14 nm processes have similar feature sizes.[22][23][21]
This is a list of processing techniques that are employed numerous times throughout the construction of a modern electronic device; this list does not necessarily imply a specific order, nor that all techniques are taken during manufacture as, in practice the order and which techniques are applied, are often specific to process offerings by foundries, or specific to an integrated device manufacturer (IDM) for their own products, and a semiconductor device might not need all techniques. Equipment for carrying out these processes is made by a handful of companies. All equipment needs to be tested before a semiconductor fabrication plant is started.[104] These processes are done after integrated circuit design. A semiconductor fab operates 24/7[105] and many fabs use large amounts of water, primarily for rinsing the chips.[106]
Additionally steps such as Wright etch may be carried out.
Wafer metrology[edit]
The highly serialized nature of wafer processing has increased the demand for metrology in between the various processing steps. For example, thin film metrology based on ellipsometry or reflectometry is used to tightly control the thickness of gate oxide, as well as the thickness, refractive index, and extinction coefficient of photoresist and other coatings.[176] Wafer metrology equipment/tools, or wafer inspection tools are used to verify that the wafers haven't been damaged by previous processing steps up until testing; if too many dies on one wafer have failed, the entire wafer is scrapped to avoid the costs of further processing. Virtual metrology has been used to predict wafer properties based on statistical methods without performing the physical measurement itself.[1]
Device yield[edit]
Device yield or die yield is the number of working chips or dies on a wafer, given in percentage since the number of chips on a wafer (Die per wafer, DPW) can vary depending on the chips' size and the wafer's diameter. Yield degradation is a reduction in yield, which historically was mainly caused by dust particles, however since the 1990s, yield degradation is mainly caused by process variation, the process itself and by the tools used in chip manufacturing, although dust still remains a problem in many older fabs. Dust particles have an increasing effect on yield as feature sizes are shrunk with newer processes. Automation and the use of mini environments inside of production equipment, FOUPs and SMIFs have enabled a reduction in defects caused by dust particles. Device yield must be kept high to reduce the selling price of the working chips since working chips have to pay for those chips that failed, and to reduce the cost of wafer processing. Yield can also be affected by the design and operation of the fab.
Tight control over contaminants and the production process are necessary to increase yield. Contaminants may be chemical contaminants or be dust particles. "Killer defects" are those caused by dust particles that cause complete failure of the device (such as a transistor). There are also harmless defects. A particle needs to be 1/5 the size of a feature to cause a killer defect. So if a feature is 100 nm across, a particle only needs to be 20 nm across to cause a killer defect. Electrostatic electricity can also affect yield adversely. Chemical contaminants or impurities include heavy metals such as iron, copper, nickel, zinc, chromium, gold, mercury and silver, alkali metals such as sodium, potassium and lithium, and elements such as aluminum, magnesium, calcium, chlorine, sulfur, carbon, and fluorine. It is important for these elements to not remain in contact with the silicon, as they could reduce yield. Chemical mixtures may be used to remove these elements from the silicon; different mixtures are effective against different elements.
Several models are used to estimate yield. They are Murphy's model, Poisson's model, the binomial model, Moore's model and Seeds' model. There is no universal model; a model has to be chosen based on actual yield distribution (the location of defective chips). For example, Murphy's model assumes that yield loss occurs more at the edges of the wafer (non-working chips are concentrated on the edges of the wafer), Poisson's model assumes that defective dies are spread relatively evenly across the wafer, and Seeds's model assumes that defective dies are clustered together.[179]
Smaller dies cost less to produce (since more fit on a wafer, and wafers are processed and priced as a whole), and can help achieve higher yields since smaller dies have a lower chance of having a defect, due to their lower surface area on the wafer. However, smaller dies require smaller features to achieve the same functions of larger dies or surpass them, and smaller features require reduced process variation and increased purity (reduced contamination) to maintain high yields. Metrology tools are used to inspect the wafers during the production process and predict yield, so wafers predicted to have too many defects may be scrapped to save on processing costs.[177]
Many toxic materials are used in the fabrication process.[185] These include:
It is vital that workers not be directly exposed to these dangerous substances. The high degree of automation common in the IC fabrication industry helps to reduce the risks of exposure. Most fabrication facilities employ exhaust management systems, such as wet scrubbers, combustors, heated absorber cartridges, etc., to control the risk to workers and to the environment.