PCI Express
PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e,[1] is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common motherboard interface for personal computers' graphics cards, sound cards, hard disk drive host adapters, SSDs, Wi-Fi and Ethernet hardware connections.[2] PCIe has numerous improvements over the older standards, including higher maximum system bus throughput, lower I/O pin count and smaller physical footprint, better performance scaling for bus devices, a more detailed error detection and reporting mechanism (Advanced Error Reporting, AER),[3] and native hot-swap functionality. More recent revisions of the PCIe standard provide hardware support for I/O virtualization.
Not to be confused with PCI-X or UCIe.Year created
2003
1 per lane (up to 16 lanes)
1 on each endpoint of each connection.[a]
Dual simplex; examples in single-lane (x1) and 16-lane (x16), per direction:
- Version 1.x: 2.5 GT/s
- x1: 250 MB/s
- x16: 4 GB/s
- Version 2.x: 5 GT/s
- x1: 500 MB/s
- x16: 8 GB/s
- Version 3.x: 8 GT/s
- x1: 985 MB/s
- x16: 15.75 GB/s
- Version 4.0: 16 GT/s
- x1: 1.97 GB/s
- x16: 31.5 GB/s
- Version 5.0: 32 GT/s
- x1: 3.94 GB/s
- x16: 63 GB/s
- Version 6.0: 64 GT/s
- x1: 7.56 GB/s
- x16: 121 GB/s
- Version 7.0: 128 GT/s
- x1: 15.13 GB/s
- x16: 242 GB/s
Yes (with ExpressCard, OCuLink, CFexpress or U.2)
Yes (with OCuLink or PCI Express External Cabling)
The PCI Express electrical interface is measured by the number of simultaneous lanes.[4] (A lane is a single send/receive line of data, analogous to a "one-lane road" having one lane of traffic in both directions.) The interface is also used in a variety of other standards — most notably the laptop expansion card interface called ExpressCard. It is also used in the storage interfaces of SATA Express, U.2 (SFF-8639) and M.2.
Format specifications are maintained and developed by the PCI-SIG (PCI Special Interest Group) — a group of more than 900 companies that also maintains the conventional PCI specifications.
Competing protocols[edit]
Other communications standards based on high bandwidth serial architectures include InfiniBand, RapidIO, HyperTransport, Intel QuickPath Interconnect, the Mobile Industry Processor Interface (MIPI), and NVLink. Differences are based on the trade-offs between flexibility and extensibility vs latency and overhead. For example, making the system hot-pluggable, as with Infiniband but not PCI Express, requires that software track network topology changes.
Another example is making the packets shorter to decrease latency (as is required if a bus must operate as a memory interface). Smaller packets mean packet headers consume a higher percentage of the packet, thus decreasing the effective bandwidth. Examples of bus protocols designed for this purpose are RapidIO and HyperTransport.
PCI Express falls somewhere in the middle, targeted by design as a system interconnect (local bus) rather than a device interconnect or routed network protocol. Additionally, its design goal of software transparency constrains the protocol and raises its latency somewhat.
Delays in PCIe 4.0 implementations led to the Gen-Z consortium, the CCIX effort and an open Coherent Accelerator Processor Interface (CAPI) all being announced by the end of 2016.[146]
On 11 March 2019, Intel presented Compute Express Link (CXL), a new interconnect bus, based on the PCI Express 5.0 physical layer infrastructure. The initial promoters of the CXL specification included: Alibaba, Cisco, Dell EMC, Facebook, Google, HPE, Huawei, Intel and Microsoft.[147]
